The pipelined CPU design for the MIPS ISA is a branch off of the single-cycle project. This project, MIPS pipelined CPU, attempts to make massive improvements to the execution time of the CPU. We decided to go with a five stage pipeline with our branch and jump handling unit in the execution stage. This project has no branch prediction and will have to flush pipes to properly execute a branch. We do later implement a forwarding unit and a hazard detection unit to handle program hazards.
MIPS Pipelined CPU
My Contribution
For this project I work on the design and implementation of the forwarding unit and the hazard detection unit. I also planned out the whole CPU architecture and made the deciding decisions on many possible approaches.
Skills & Knowledge Gained
Technical skills I improved/learned are:
- Git, Github, and Gitlab
- VHDL
- Questasim
- Processor Design