The single-cycle CPU design for the MIPS ISA is a straightforward and efficient processor architecture where each instruction is executed within a single clock cycle. This approach simplifies the control logic and allows for predictable and consistent instruction execution times. The CPU fetches instructions from memory, decodes them, performs necessary operations in an arithmetic logic unit (ALU), and stores the results all within one cycle. Key components include instruction memory, a control unit, an ALU, data memory, and registers for temporary data storage.
MIPS Single Cycle CPU
My Contribution
For this project I work on the design and implementation of many of the major components for this CPU like the ALU and register file.
Skills & Knowledge Gained
Technical skills I improved/learned are:
- Git, Github, and Gitlab
- VHDL
- Questasim
- Processor Design